Xilinx Virtex UltraScale FPGA

The Xilinx UltraScale FPGAs are built on 20 nm process technology and provide ASIC-like clocking for scalability, performance, and lower dynamic power. The Virtex devices feature two types of multi-gigabit transceivers: 32x 16Gb/s (GTH) and 16x 32.75 Gb/s (GTY). The GTY transceivers enable 400GbE, 100GbE, and 25GbE. The FPGA also supports up to 1,800 DSP slices. The UltraScale FPGAs provide four integrated blocks for PCI Express, supporting x8 Gen3 Endpoint and Root Port designs. Integrated blocks for 150 Gb/s Interlaken and 100 Gb/s Ethernet (100G MAC/PCS) enable simple, reliable support for Nx100G switch and bridge applications.

I/O Interfaces

The XUSP3R provides a variety of interfaces for high-speed serial I/O as well as debug support. Four QSFP28 cages are available on the front panel, each supporting 100GbE, 40GbE, four 25GbE, or four 10GbE channels, for a total of up to 400 Gbps of bandwidth. The four QSFPs can also be combined for 400GbE. The QSFP channels are connected directly to the UltraScale FPGA via 32 Gb/s GTY transceivers. The QSFP cages can optionally be adapted for SFP+.

Two Gen3 x8 PCIe interfaces connect to the FPGA via 16 GTH transceivers, allowing for a x8 PCIe connection in a standard slot or two x8 interfaces in a bifurcated slot. An optional serial expansion interface provides a 16x GTH transceiver port connection to the FPGA and can be used to add serial memory, such as Hybrid Memory Cube (HMC). The expansion site can also be used to connect an additional two x8 PCIe interfaces to the FPGA via a cable assembly connecting to an adjacent board that supports PCIe bifurcation, allowing for a total of four x8 PCIe interfaces.

A USB 2.0 interface is available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input.

Memory

The XUSP3R features four DIMM sites that support standard DDR4 DIMMs and proprietary QDR-II+ DIMMs. Each DIMM site supports up to 64 GBytes of DDR4 with optional ECC or up to 72 MBytes QDR-II+ (2 banks x18). Additional on-board memory includes Flash with factory default and support for multiple FPGA images.

Board Management Controller

The XUSP3R features an advanced system monitoring subsystem, similar to those typically found on today’s server platforms. At the heart of the board’s monitoring system lies a Board Management Controller (BMC), which accepts Intelligent Platform Management Interface (IPMI) messaging protocol commands. The BMC provides a wealth of features, including control of power and resets, monitoring of board sensors, FPGA boot loader, voltage overrides, configuration of programmable clocks, access to I2C bus components, field upgrades, and IPMI messaging. Access to the BMC is via PCIe or USB. BittWare’s BittWorks II Toolkit also provides utilities and libraries for communicating with the BMC components at a higher, more abstract level, allowing developers to remotely monitor the health of the board.

BwMonitor in the BittWorks II Toolkit provides a view into the board management capabilities of your BittWare hardware.

Development Tools

BittWorks II Toolkit

BittWare offers complete software support for the XUSP3R with its BittWorks II software tools. Designed to make developing and debugging applications for BittWare’s boards easy and efficient, the Toolkit is a collection of libraries and applications that provides the glue between the host application and the hardware. A variety of features allow developers to take full advantage of the Xilinx UltraScale FPGA capabilities on the BittWare board, including FPGA control via PCIe, Flash programming, custom ISR scripts, and convenient control of FPGA loads. The Toolkit supports 32-bit, and 64-bit Windows and Linux platforms and can connect to the board via PCIe or USB, providing a common API no matter the connection method.

FPGA Development Kit

BittWare’s FPGA Development Kit (FDK) provides FPGA board support IP and integration for BittWare’s FPGA-based boards. The FDK includes FPGA components that provide preconfigured physical interfaces, infrastructure, and examples, drastically cutting development time and easily integrating into existing FPGA development environments.

Working example projects are available for each board which illustrate how to move data between the board’s different interfaces. Supported interfaces include DDR4, QDR-II+, PCIe, 10GbE, LVDS, SerDes, and Double Data Rate I/O.

FPGA

  • Up to 1.9 million logic elements
  • Up to 132 Mb of embedded memory
  • Up to 4 integrated PCIe cores
  • Up to 1,800 DSP slices with 27×18 multipliers
  • Xilinx UltraScale FPGA
    • Virtex UltraScale125/160/190
  • Multi-gigabit transceivers
    • 16x GTY at 32.75 Gbps and 32x GTH at 16 Gbps

On-Board Memory

  • Flash memory for booting FPGA

Optional DIMM Memory

  • 4 DIMM sites, each supporting*:
    • Up to 64 GBytes DDR4 x72 with ECC
    • Up to 576 Mbits QDR-II x18

PCIe Interface

  • Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGA (One x8 interface in a standard slot; two x8 interfaces requires bifurcated slot)
  • Serial Expansion Port can be used for two additional x8 interfaces

USB Header

  • Micro USB port (USB 2.0) for debug and programming FPGA and Flash

QSFP Cages

  • 4 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 GTY transceivers
  • Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 10GbE and can be combined for 400GbE
  • Backward compatible with QSFP and can be optionally adapted for use as SFP+

Serial Expansion Port

  • Expansion interface to FPGA via 16x GTH transceivers (optional; requires second slot)

Timestamping

  • 1 PPS input
  • Reference clock input

Board Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • 3/4-length, standard-height PCIe dual slot card
  • 241mm x 111.15mm
  • Max. component height: 34.79mm dual slot

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; Matlab API; source code porting kit also available

FPGA Development

  • FPGA Development Kit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example projects
    • Software components and drivers
  • Xilinx Tools
    • Vivado® Design Suite
    • USB to JTAG converter
XUSP3R – RW-ABBBBCD-EEFFGGHH-IJKLMNOP-QR-S-T
RW Ruggedization

0U = Commercial (0°C to 50°C)*
A UltraScale Printed Wiring Board

D = Optimized for VU190 FPGA*
BBBB FPGA Type and Size

  • 190V = Virtex VU190*
C FPGA Core Speed Grade

  • 1 = Slower
  • 2 = Standard*
  • 3 = Faster
D FPGA Temperature Range

E = Extended (Tj = 0 to +100C)*
EE DIMM 1‡

  • 00 = None*
  • R4 = DDR4 16GB RDIMM
  • R5 = DDR4 32GB RDIMM
  • R7 = DDR4 128GB RDIMM
  • L5 = DDR4 32GB LRDIMM
  • L6 = DDR4 64GB LRDIMM
  • Q4 = Dual QDRII+ x18 144Mb
  • Q5 = Dual QDRII+ x18 288Mb
FF DIMM 2‡

  • 00 = None*
  • R4 = DDR4 16GB RDIMM
  • R5 = DDR4 32GB RDIMM
  • R7 = DDR4 128GB RDIMM
  • L5 = DDR4 32GB LRDIMM
  • L6 = DDR4 64GB LRDIMM
  • Q4 = Dual QDRII+ x18 144Mb
  • Q5 = Dual QDRII+ x18 288Mb
GG DIMM 3‡

  • 00 = None*
  • R4 = DDR4 16GB RDIMM
  • R5 = DDR4 32GB RDIMM
  • R7 = DDR4 128GB RDIMM
  • L5 = DDR4 32GB LRDIMM
  • L6 = DDR4 64GB LRDIMM
  • Q4 = Dual QDRII+ x18 144Mb
  • Q5 = Dual QDRII+ x18 288Mb
HH DIMM 4‡

  • 00 = None*
  • R4 = DDR4 16GB RDIMM
  • R5 = DDR4 32GB RDIMM
  • R7 = DDR4 128GB RDIMM
  • L5 = DDR4 32GB LRDIMM
  • L6 = DDR4 64GB LRDIMM
  • Q4 = Dual QDRII+ x18 144Mb
  • Q5 = Dual QDRII+ x18 288Mb
I Oscillator

S = Standard
J Auxilliary Oscillator

0 = 322.265625*
K Timing

  • S = Front panel SMAs (in adj. slot)
  • X = On-board circuits only*
L QSFP Configuration

4 = 4 QSFP cages
M Serial Expansion Port

  • 0 = Not Installed
  • 1 = Installed*
N Factory JTAG Header

  • 0 = Not Installed*
  • 1 = Installed
O USB-to-JTAG

  • 0 = Not Installed
  • 1 = Installed*
P Heatsink

  • 3 = Active 2-slot*
  • 4 = Passive 2-slot
Q Misc. Configuration

0 = Default
R Power Supply

  • R = Right angle connector*
  • V = Vertical connector
S Mechanical Options

  • 0 = No stiffener
  • S = Standard stiffeners*
T Assembly

6 = RoHS 6/6
BittWare Feature UltraScale Family
Program Flash via PCIe via USB
Configure FPGA From Flash via PCIe via USB
Configure FPGA Directly via USB
Reset FPGA via PCIe via USB ✓ ✓
Access FPGA Registers, Memory Spaces From User Applications via PCIe via USB ✓ ✗
Virtual PCIe Hot-Swap
On-board JTAG Pod
Factory Backup Image with PCIe
Multiple User Images in Flash
Serial Number via PCIe via USB ✓ ✓
MAC Addresses For Each Network Interface via PCIe via USB ✓ ✓
BMC Voltage, Current, Temperature Sensors via PCIe via USB ✓ ✓
BMC Clock Re-programming via PCIe via USB
BMC FPGA Core Voltage Override via PCIe via USB
Upgrade BMC Firmware via PCIe via USB ✗ ✓
Documentation Quick-start Guide User’s Manual How-to Index BMC User’s Guide ✓ ✓ ✓ ✓
Examples PCIe DMA 10G Ethernet DDR4 Memory BMC Host (without using BittWare drivers) ✓ ✓ ✓ ✓